1. Field of the Invention
The present invention relates generally to integrated circuits, more particularly to complementary metal oxide semiconductor integrated circuit switching devices, and more specifically to a ratio-less, high voltage, CMOS, switch for non-volatile memory, address data decoding, integrated circuit devices.
2. Description of Related Art
Complementary metal oxide silicon (xe2x80x9cCMOSxe2x80x9d) technology is a preferred fabrication process for many integrated circuit (xe2x80x9cICxe2x80x9d) devices, particularly those in which low power consumption and high component density are priorities. Many publications describe the details of common techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures; see e.g., Silicon Processes, Vol. 1-3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation (assignee herein), Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and common fabrication step techniques will be referred to hereinafter as simply: xe2x80x9cin a known manner.xe2x80x9d The commonly used term xe2x80x9cchipxe2x80x9d is used to refer to an entire IC device. As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art.
In programmable non-volatile memory cells, such as row and column address decoder outputs, it is generally known to use a circuit that switches a relatively high voltage to the output based on a relatively low voltage input for an addressed cell. It will be recognized by those skilled in the art that such xe2x80x9cswitchxe2x80x9d circuits (any electronic circuit that reverses and maintains a state, namely HIGH/LOW or 1/0, each time the input power changes) can have many other uses, such as signal level translators, output pad drivers, programming circuits, and the like.
FIG. 1 (Prior Art) is an electrical schematic of a typical IC, non-volatile memory, address decoder output, high voltage switching circuit 100, xe2x80x9chigh V switchxe2x80x9d for short. Four metal-oxide-silicon field effect transistors (xe2x80x9cMOSFETxe2x80x9d), N1, N2, P1 (n-well device), P2 (n-well device) and an inverter are used. [It will be recognized by those skilled in the art that all dopant types can be reversed]. The high V switch receives an input Enable signal, xe2x80x9cEn,xe2x80x9d having a transition either from LOW-to-HIGH or HIGH-to-LOW (e.g., between a zero volt LOW and a two-and-a-half volt HIGH or other logic power supply voltage, xe2x80x9cVcc,xe2x80x9d depending on the fabrication process design), and provides an output signal xe2x80x9cOUTxe2x80x9d that needs to be driven correspondingly (e.g., between a zero volt LOW and a thirteen volt HIGH or other generated fabrication process design level). The power supply to the circuit is a high voltage, xe2x80x9cVpp,xe2x80x9d generated internally by other known manner circuitry of the IC (not shown), e.g., the desired output level, thirteen volts. In operation, when signal En is LOW, the inverter output, INV, is HIGH and transistor N2 is ON, transistor P1 is ON, transistors N1 is OFF and P2 are OFF (gate and source at Vpp), so OUTB is at Vpp and the signal OUT is switched to LOW. Note that N1 and P1 must be. designed in relative size to have a size ratio wherein N1 is a much larger individual device than P1; similarly the size of N2 greater than  greater than P2. Thus, when signal En goes HIGH/Vcc, the inverter output goes LOW and N2 is OFF, N1 being ON overcomes P1, OUTB is pulled LOW, turning ON P2 which feeds back into P1 also trying to shut P1 OFF, P2 being ON is passing Vpp to switch the OUT signal node (and at the same time also turning OFF P1). In other words, to make the signal transition with this conventional circuit, the N1 and N2 devices have to overcome P1 and P2 devices so they must be much larger in design, using valuable IC chip space. Depending on the process and device parameters N1 and N2 may be as much as five times as large as P1 and P2. Thus, this circuit is also relatively slow. Moreover, during this difficult transition, excessive power is used. Furthermore, the individual devices must be built to handle the high voltage without breakdowns (grounded gate (e.g, in FIG. 1 when N1 is OFF, having the gate at LOW and the source grounded, yet the OUT node is at Vpp at the start of an En LOW and INV transition to 1), n-well (e.g., in the p-type devices, the n-well is tied to Vpp), n+/p+ junction breakdowns), such as by having relatively very thick ( greater than 250 Angstroms) gate oxide to handle the high voltage levels, complicating fabrication process steps.
It is common to shorthand the system function via a logic table, such as Table 1, also provided for the remaining Figures discussed:
Another prior art high voltage switch circuit is shown in FIG. 2 (Prior Art). This circuit is designed to handle grounded gate problems via a cascode arrangement of MOSFET transistors. Cascoded N3 and N4 are connected at their respective gates to Vcc. The respective drain electrodes at N1 and N2 never reach Vpp but when the signal OUT node or the signal OUTB node is raised to Vpp, the drain electrodes are only at Vccxe2x88x92Vtn, where Vt is the threshold voltage for the n-type MOSFETS, thus, the drain-source voltage, Vds, remains smaller than Vpp. Thus grounded gate breakdown is no longer a problem. Obviously, however, even more chip real estate is required than for the circuit of FIG. 1. For the p-channel devices, cascoded P3 and P4 are tied to a gate bias voltage, GBIAS. That bias voltage is strategically selected according to design parameters to prevent grounded gate breakdown in the pull-up side of the circuit. However, to switch the switch, a timing sequence must be implemented, thus complicating design. In other words, initially to decode the correct En signal transition, GBIAS is held at zero volts until an En transition when signal OUTB is HIGH, then raise Vpp and GBIAS levels. Note also that the n-wells of the p-type devices P1-4 are again tied to Vpp, but P3 and P4 are not source-tied to Vpp; therefore, separate n-wells are required, again adding design and fabrication complexity. Note also, the series-coupled extra transistors on both sides of the switch will be an inherently slower reacting circuit. Also this design still requires N-to-P size ratios because each N-stack must overcome the respective P-stack connected in series thereto to flip the switch between HIGH/LOW states. Thus, design and area complexity is a main drawback to this solution to the problems with high voltage CMOS switch circuits.
There is a need for a faster, small, simpler design for a high voltage CMOS switch.
In its basic aspects, the present invention provides a high voltage CMOS switch including: first devices for signal switching coupled to an input electrode, having a first logic state and a second logic state, and arranged as a parallel-connected, cascode input device and biased at a first electrical potential; and second devices for signal switching, coupled to said first devices and to a second electrical potential greater than said first electrical potential and to an output electrode, and arranged as a parallel-connected cascode output device coupled to said input electrode such that said second devices is pre-biased to said first electrical potential such that switching occurs at the output from said first electrical potential to said second electrical potential without said first devices being required to over-drive said second devices.
In another aspect, the present invention provides a high voltage switch circuit device, including: an input node; a first output node; a second output node; a first source of electrical potential level; a second source of electrical potential level greater than the first source of electrical potential; an inverter connected to the input node; a first cascode, biased by said first source of electrical potential level, connected to said input node; a second cascode biased by said first source of electrical potential, and connected in series via the inverter with the first cascode, the second cascode connected to said output node; a third cascode, biased by a signal on the input node, connected in series with the first cascode, and connecting said second source of electrical potential level to said first output node; a fourth cascode, biased by an output signal of the inverter, connected in series with the second cascode, and connecting said second source of electrical potential level to said second output node, wherein a transition of a signal level between a reference and a second state equal to said first source of electrical potential level on said input node causes a transition on said output node between said first source of electrical potential level and said second source of electrical potential level without said first cascode having to over-drive said third cascode and without said second cascode having to over-drive said fourth cascode.
In another aspect, the present invention provides a memory decoder circuit including a high voltage switch device comprising: first devices for signal switching coupled to an input electrode, having a first logic state and a second logic state, and arranged as a parallel-connected, cascode input device and biased at a first electrical potential; and second devices for signal switching, coupled to said first devices and to a second electrical potential greater than said first electrical potential and to an output electrode, and arranged as a parallel-connected cascode output device coupled to said input electrode such that said second devices is pre-biased to said first electrical potential such that switching occurs at the output from said first electrical potential to said second electrical potential without said first devices being required to over-drive said second devices.
Some of the advantages of the present invention are:
it is a ratio-less MOSFET design;
it has built-in grounded gate breakdown protection when required;
it minimizes chip real estate requirements;
it is a relatively faster switch;
it requires no external, global bias;
it is a self-biased cascode;
it operates a very low Vcc compared to state of the art devices; and
it has a plurality of uses.
The foregoing summary and list of advantages is not intended by the inventor(s) to be an inclusive list of all the aspects, objects, advantages and features of the present invention nor should any limitation on the scope of the invention be implied therefrom. This Summary is provided in accordance with the mandate of 37 C.F.R. 1.73 and M.P.E.P. 608.01(d) merely to apprise the public, and more especially those interested in the particular art to which the invention relates, of the nature of the invention in order to be of assistance in aiding ready understanding of the patent in future searches. Other objects, features and advantages of the present invention will become apparent upon consideration of the following explanation and the accompanying drawings, in which like reference designations represent like features throughout the drawings.